In optical communications, the transmitted signal over a fiber optic link will exhibit an asymmetric eye opening. For example, as depicted in FIG. 1A, a transmitted signal exhibits an asymmetric eye relative to vertical threshold of its sampler. As known to one skilled in the art, LOGIC 0 has significantly less vertical margin compared to LOGIC 1 due to the shown asymmetry. One way to alleviate the problem is to adjust the Direct Current (DC) component voltage levels of the single-ended signals Outp and Outn in order to level out the vertical margins of Outp and Outn with respect to the sampler. In the example of FIG. 1A, one can decrease the DC component voltage level of Outp, or increase the DC component voltage level of Outn to substantially reduce the asymmetric eye opening. This adjustment of the DC component voltage levels can also be done by both decreasing the DC component voltage level of Outp and increasing the DC component voltage level of Outn simultaneously and in a differential manner for half the amount at each side.
In order to optimize the performance of the receiver to capture the incoming signal with an asymmetric eye opening, it is required to establish a threshold adjustment mechanism that can adjust the vertical eye opening of the signal to a more balanced and symmetric shape. As seen in FIG. 1B, after threshold adjustment, vertical margin of LOGIC 0 is increased and vertical margin of LOGIC 1 is reduced, compared to the same margins in FIG. 1A. Since the minimum margin level determines the receiver performance, it is always desirable to have balanced vertical margins or symmetric eye opening. Threshold adjustment circuits are designed to achieve a more symmetric eye opening in the incoming signals.
FIG. 2 is a conventional threshold adjustment circuit. As depicted in FIG. 2, two current-based Digital to Analog Converters (DACs) are directly connected to Outp and Outn decrease the DC component voltage level of Outp, or increase the DC component voltage level of Outn. However, in this configuration, the DACs' outputs have significant capacitive loading due to large DAC transistors needed to generate the required maximum current for the threshold adjustment. In this case, the DACs heavily load Outp and Outn and thus causing bandwidth limitation. Moreover, two current DACs occupy large silicon area.
In another typical threshold adjustment circuit shown in FIG. 3, two switches Sp and Sn connected to a single current DAC are used to connect the single DAC to Outp or Outn, alternatively. This scheme also suffers from bandwidth limitation due to heavy capacitive loading of Outp and Outn. Switches Sp and Sn can be considered as transistors in triode region when turned ON. In the triode region, Sp and Sn exhibit large drain capacitances, as well as low drain-to-source resistance (Rds). Due to low Rds resistance, majority of the DAC output capacitance will also be observed at Outp and Outn. In a case where low voltage transistors are being used with a supply voltage (VDD) above the reliability voltage limit, Sp and Sn switches may exhibit reliability problems due to over the limit terminal voltages.
All of above conventional implementations introduce bandwidth limitations on the signal path. In addition, the above conventional threshold adjustment circuits require further improvements to avoid any reliability problems if low voltage transistors are used with a power supply voltage above their reliability voltage limit. These circuits also occupy large silicon area.
Therefore, there is a need for an accurate and reliable threshold adjustment circuit that does not impose any significant bandwidth reduction due to loading of the signal path.